MIPS: Break out of cache loops for unimplemented caches

MIPS: Break out of cache loops for unimplemented caches

If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by generalising the check for a zero line size & avoiding the cache
op loop when this is the case.

Signed-off-by: Paul Burton <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Cc: [email protected]